Priority encoder circuits can receive multiple signals, and prioritize such signals according to a predetermined order. In addition, a highest priority signal can be represented by a digital value, typically corresponding to a physical location generating the highest priority signal. Priority encoder circuits are often used in content addressable memory (CAM) devices to prioritize match indications, and thereby identify a highest priority match result.
A conventional priority encoder circuit is shown in FIG. 9 and designated by the general reference character 900. Priority encoder circuit 900 can be one of many such circuits, each of which prioritizes its own local set of match indications. As such, priority encoder circuit 900 can be considered a “local” priority encoder (LPE) circuit. Conventional LPE circuit 900 can receive “n” encoder input signals 902, arbitrarily shown in groups of four in FIG. 9. An “n×n” priority encoder logic circuit 904 can prioritize active input signals to generate n corresponding prioritized output signals 906. Only one highest priority signal will be activated in response to one or more active input signals. In the conventional LPE circuit 900 n prioritized output signals 906 can be fed into a read only memory (ROM) 908. A ROM 908 can include n locations each accessible by a corresponding prioritized output signal. Locations of ROM 908 can encode each n prioritized output signal into a unique log2(n) digital value.
In order to prioritize from among the “n” encoder input signals 902, priority encoder logic 904 must “suppress” any active input signals of lower priority. As a result, in a prioritizing operation, the status of a highest priority encoder input signals 902 must “percolate” down through “n” lower priority inputs. This can contribute to delay between the time one or more active input signals is received and the generation of a ROM output value.